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40 nm electron beam patterning and its application to silicon nano-structure fabrication

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5 Author(s)
Sangyeon Han ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; Taejnn Park ; Bonkee Kim ; Hyungcheol Shin
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We report on 40 nm patterning using an E-beam lithography system. SAL601 negative E-beam resist was used for this experiment. In order to utilize the maximum ability of the E-beam system, we reduced the PR thickness to 100 nm, and the field size to 200 μm. In this way, PEB (Post Expose Bake) time and temperature, which are very important factors for nanopatterning, were reduced for minimum line width. In addition, digitizing was optimized for better results. Quantum wires, quantum dots, and quantum dots on a narrow channel, which can be used for nano-scale memory devices (such as single electron memory devices), were fabricated using these lithography techniques

Published in:

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Date of Conference:

1999