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High aspect ratio via etching for dual damascene process in a inductively coupled plasma (ICP) etcher

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5 Author(s)
Kuk-Han Yoon ; Res. Center, Hyundai Micro Electron. Co. Ltd., Cheongeju, South Korea ; Woo-Sung Cho ; Jae-Hyun Park ; Jae-Hee Ha
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Deep-via etching for a dual-damascene process adopting a via-first scheme was studied in an ICP etching system. Via etching in a structure compatible with 0.18 μm design rules requires process specifications such as high aspect ratio IMD (inter-metal dielectric) etching consisting of intermediate nitride and oxide layers, highly selective etching to photoresist (PR) and to the sub-underlying layer. In order to investigate the compromise between the main etch parameters, a statistical experimental design was performed. Oxide (TEOS) etch rate and selectivity to PR were evaluated as main responses and dc bias voltage was also monitored. PR selectivity increased with CO and CH2F2 gas flow rate, but pressure and top power have little effect on it. TEOS etch rate went up in proportional to top power, but CO gas flow rate and pressure showed a reverse trend. Additionally, while TEOS etch rate was inversely proportional to dc bias voltage, PR selectivity was independent of it. The optimized process conditions were applied to real deep via structures. Since both unselective etching for the intermediate nitride layer and highly selective etching for the sub-underlying layer were desired, two step etching was indispensable. Consequently, a vertical via profile with an aspect ratio of 5.3 was achieved through the IMD layers

Published in:

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Date of Conference:

1999

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