By Topic

Wallace-tree based timing-driven synthesis of arithmetic circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Junhyung Um ; Dept. of Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Taewhan Kim

Wallace-tree style implementations have been proven to be effective schemes for fast computations of arithmetic. This paper generalizes the concept of Wallace's scheme to include `uneven' arrival times of input operands of the arithmetic circuit. More specifically, for an arithmetic expression in the circuit, we proposed a synthesis algorithm for solving the problem of transforming the expression into a form of the Wallace-tree structure that leads to a minimal timing of the circuit. This practically enables an extensive utilization of Wallace's scheme over the arithmetic circuit, thereby reducing the timing of circuit more effectively. Experimental results are provided to show the effectiveness of the proposed algorithm, over the conventional two-step (RTL and logic) optimization

Published in:

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Date of Conference: