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A high speed transmission/reception circuit for HDTV encoder based on parallel FIFO structure

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3 Author(s)
Chen Yingqi ; Inst. of Image Commun. & Inf. Process., Shanghai Jiaotong Univ., China ; Yang Xiao Kang ; Yu Songyu

A data transmission/reception circuit based on parallel FIFO storage structure is introduced. It is used as a video data testing source for an HDTV encoder or used for encoded data test and analysis. It is designed for being inserted in a PC's AT bus. Under the control of a PC, it can transmit or receive data at very high speed. Its function, structure, characteristics and limits are explained, especially some design methods and design thoughts for increasing speed and storage scale as well as decreasing cost. The test results are also given.

Published in:

Communications, 1999. APCC/OECC '99. Fifth Asia-Pacific Conference on ... and Fourth Optoelectronics and Communications Conference  (Volume:2 )

Date of Conference:

18-22 Oct. 1999

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