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The TigerSHARC DSP architecture

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2 Author(s)
Fridman, J. ; Analog Devices Inc., Norwood, MA, USA ; Greenfield, Z.

This highly parallel DSP architecture based on a short-vector memory system incorporates techniques found in general-purpose computing. It promises sustained performance close to its peak computational rates of 900 MFLOPS (32-bit floating-point) or 3.6 BOPS (16-bit fixed-point)

Published in:

Micro, IEEE  (Volume:20 ,  Issue: 1 )