By Topic

EPIC: Explicitly Parallel Instruction Computing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Schlansker, M.S. ; Hewlett-Packard Labs., USA ; Rau, B.R.

Over the past two and a half decades, the computer industry has grown accustomed to the spectacular rate of increase in microprocessor performance. The industry accomplished this without fundamentally rewriting programs in parallel form, without changing algorithms or languages, and often without even recompiling programs. Instruction level parallel processing achieves high performance without major changes to software. However, computers have thus far achieved this goal at the expense of tremendous hardware complexity-a complexity that has grown so large as to challenge the industry's ability to deliver ever-higher performance. The authors developed the Explicitly Parallel Instruction Computing (EPIC) style of architecture to enable higher levels of instruction-level-parallelism without unacceptable hardware complexity. They focus on the broader concept of EPIC as embodied by HPL-PD (formerly known as HPL PlayDoh) architecture, which encompasses a large space of possible EPIC ISAs (instruction set architectures). In this article, the authors focus on HPL-PD because it represents the essence of the EPIC philosophy while avoiding the idiosyncracies of a specific ISA

Published in:

Computer  (Volume:33 ,  Issue: 2 )