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A low power /spl Sigma//spl Delta/ analog-to-digital modulator with 50 MHz sampling rate in a 0.25 /spl mu/m SOI CMOS technology

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7 Author(s)
Swaminathan, A. ; Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada ; Fong, N. ; Lauzon, P. ; Hong-Kui Yang
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A second-order double-sampled analog-to-digital /spl Sigma//spl Delta/ modulator is implemented in a 0.25 /spl mu/m fully-depleted silicon-on-insulator (FDSOI) CMOS process. FDSOI has a better subthreshold swing and reduced short-channel effect compared to traditional bulk CMOS, and therefore the threshold voltage and hence the supply voltage can be lowered for low power applications.

Published in:

SOI Conference, 1999. Proceedings. 1999 IEEE International

Date of Conference:

4-7 Oct. 1999

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