By Topic

Generation of optimised fault lists for simulation of analogue circuits and test programs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
A. Milne ; Huddersfield Univ., UK ; D. Taylor ; J. Saunders ; A. D. Talbot

The definition of a universally acceptable analogue fault model has been a major obstacle to the acceptance, by industry, of any of the new test and testability techniques that have been proposed for analogue and mixed-signal circuits. This is largely because analogue faults are difficult to model and very time consuming to simulate. Previous independent research has demonstrated how inductive fault analysis can be used to reduce the size of a fault set and how circuit sensitivity analysis can be employed to ascertain what constitutes a fault for each circuit component. The authors combine these two principles by first employing an inductive fault analysis to eliminate faults which are unlikely to occur from the fault set, and then employing a circuit sensitivity analysis to eliminate from the remaining set `faults' which have no effect on circuit functionality. As a result, fault simulation becomes a significantly less onerous task and the evaluation and comparison of test programs and techniques can be achieved much more conveniently

Published in:

IEE Proceedings - Circuits, Devices and Systems  (Volume:146 ,  Issue: 6 )