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Models that place design constraints on devices which are used to measure the leakage currents in high-resistivity semiconductor materials are presented. If these design constraints are met, these models can then be used to quantitatively predict the surface sheet resistance of devices which are dominated by surface leakage currents. As a result, a means is provided to directly compare passivation techniques which are developed to decrease surface leakage currents. Furthermore, these models illustrate the necessity for inclusion of relevant geometrical data on sample size and shape and electrode configuration when reporting results of surface passivation techniques. These models specifically examine the case where a DC potential is applied across two electrodes on the surface of a semiconductor substrate which has a surface layer with lower resistivity than the bulk material. We describe several of the more common configurations used in analyzing passivation techniques for compounds of Cd/sub 1-x/Zn/sub x/Te (CZT) used for room-temperature radiation detection.