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Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND memory

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3 Author(s)
Ikehashi, T. ; MicroElectron. Eng. Lab., Toshiba Corp., Yokohama, Japan ; Imamiya, K. ; Sakui, K.

With the use of a device simulator, we show that an ESD protection circuit whose junction is filled with contacts is suited to a scaled STI process with thin n/sup -/ junctions with n/sup +/ being implanted from contact holes. We have confirmed by measurements of the CMOS NAND flash memory that the protection has sufficient robustness.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999

Date of Conference:

28-30 Sept. 1999

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