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Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips

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7 Author(s)
Voldman, S. ; Div. for IBM Microelectron., IBM Corp., Essex Junction, VT, USA ; Hui, D. ; Warriner, L. ; Young, D.
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This paper discusses the electrostatic discharge (ESD) robustness of silicon-on-insulator (SOI) high-pin-count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes without the need for additional masking steps, process implants or ESD design area.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999

Date of Conference:

28-30 Sept. 1999