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CMOS stress sensors on [100] silicon

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5 Author(s)
R. C. Jaeger ; Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA ; J. C. Suhling ; R. Ramani ; A. T. Bradley
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CMOS analog stress sensor circuits based upon the piezoresistive behavior of MOSFET's are presented. On the [100] surface, these circuits provide temperature-compensated outputs that are proportional to the in-plane normal stress difference (/spl sigma/(11)'-/spl sigma//sub 22/') and the in-plane shear stress /spl sigma//sub 22/'. The circuits provide high sensitivity to stress, well-localized stress-state measurement, and direct voltage or current outputs that eliminate the need for tedious /spl Delta/R/R measurements required with more traditional resistor rosettes. The theoretical and experimental results also provide design guidance for calculating and minimizing the sensitivity of traditional analog circuits to packaging-induced die stress.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:35 ,  Issue: 1 )