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A data-replace-controlled cache memory system and its performance evaluations

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3 Author(s)
N. Maki ; Grad. Sch. of Inf. Syst., Univ. of Electro-Communs., Tokyo, Japan ; K. Hoson ; A. Ishida

We present a novel cache memory system to reduce cache miss ratio. It enables the cache to lock or release the data in it by software controls. The paper describes its overall hardware and programming directions and also shows performance evaluations. The results show that the computer with this system can reduce the cache misses by up to 60.9% and can execute faster than a computer with a conventional cache

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TENCON 99. Proceedings of the IEEE Region 10 Conference  (Volume:1 )

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