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A 3.3 V CMOS PLL with a two-stage self-feedback ring oscillator

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2 Author(s)
Yeon Kug Moon ; Dept. of Electron. Eng., Inha Univ., Inchon, South Korea ; Kwang Sub Yoon

A 3.3 V PLL (phase locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of VCO (Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30 MHz-1 GHz with a good linearity. The DC-DC voltage up/down converter is newly, designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 μm n-well CMOS process. The simulation results show a locking time of 2.6 μsec at 1 GHz, lock in range of 100 MHz-1 GHz, and a power dissipation of 112 mW

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TENCON 99. Proceedings of the IEEE Region 10 Conference  (Volume:1 )

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