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High-voltage devices for 0.5-μm standard CMOS technology

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3 Author(s)
C. Bassin ; Electron. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland ; H. Ballan ; M. Declercq

The feasibility of the smart voltage extension (SVX) technique featuring complementary high-voltage devices without any modifications of the process steps of an 0.5-μm standard CMOS technology is discussed here. This letter focuses on the optimization of the breakdown voltage of the HVNMOS as well as the possible implementation of the HVPMOS. Different high-voltage options with increasing process modification steps are discussed as a function of the required high-voltage capabilities.

Published in:

IEEE Electron Device Letters  (Volume:21 ,  Issue: 1 )