Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Clock multiplier using digital CMOS standard cells for high-speed digital communication systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Youngkou Lee ; Dept. of Inf. & Commun, KJIST, Kwangju, South Korea ; Sungsoo Choi ; Seung-Geun Kim ; Jeong-A Lee
more authors

The authors propose and evaluate the performance of a 2N times clock multiplier that controls memory components for high-speed data communications. To improve the reliability of the circuit, a symmetric circuit structure is used, while to verify circuit operation by means of a simple method, an MVU estimator is found from simulation data. The proposed circuit can provide clock rates, which are usually required in the multiple phase shift keying (MPSK) or multiple quadrature amplitude modulation (MQAM) modulation schemes, of 2 to 2N times that of the input clock

Published in:

Electronics Letters  (Volume:35 ,  Issue: 24 )