Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Demodulating binary phase shift keyed signals using programmable logic devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
Kikkert, C.J. ; Dept. of Electr. & Comput. Eng., James Cook Univ., Townsville, Qld., Australia ; Blackburn, C.

This paper describes the realisation of a differential BPSK demodulator using a high speed ADC, an EPLD and an EPROM. By incorporating both I and Q data in the demodulation process, a significant improvement in performance is obtained. Computer simulation shows the bit error rate (BER) performance versus received carrier to noise ratio (CNR) is virtually identical to the theoretical performance of a differential phase shift keyed (DPSK) detector. The realisation of the special PLL required, to recover the data clock using an EPLD, a DAC, a conventional loop filter and VCO is described

Published in:

Signal Processing and Its Applications, 1999. ISSPA '99. Proceedings of the Fifth International Symposium on  (Volume:2 )

Date of Conference:

1999