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Demodulating binary phase shift keyed signals using programmable logic devices

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2 Author(s)
Kikkert, C.J. ; Dept. of Electr. & Comput. Eng., James Cook Univ., Townsville, Qld., Australia ; Blackburn, C.

This paper describes the realisation of a differential BPSK demodulator using a high speed ADC, an EPLD and an EPROM. By incorporating both I and Q data in the demodulation process, a significant improvement in performance is obtained. Computer simulation shows the bit error rate (BER) performance versus received carrier to noise ratio (CNR) is virtually identical to the theoretical performance of a differential phase shift keyed (DPSK) detector. The realisation of the special PLL required, to recover the data clock using an EPLD, a DAC, a conventional loop filter and VCO is described

Published in:

Signal Processing and Its Applications, 1999. ISSPA '99. Proceedings of the Fifth International Symposium on  (Volume:2 )

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