By Topic

Test and measurement [Technology 2000 analysis and forecast]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

The awareness that every electronic product, from PCs to Internet appliances, is pining for tinier and more powerful chips is whipping semiconductor development along at a frenetic pace. It is also hounding automation of design and test and IC test development, but test inevitably lags behind chip development. Devising (and performing) tests for the so-called system on a chip is a time-consuming process. Many thousands of test patterns and vectors must be created, as must protocols, and the fault coverage achieved must be high enough to complete the necessary testing and to minimize the cost. The challenges multiply further as the test chain ascends from chip to board to system and ultimately field-level tests. Each level adds expense so that soon, by some estimates, test could account for half of the final cost of a chip

Published in:

Spectrum, IEEE  (Volume:37 ,  Issue: 1 )