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Void-effect modeling of flip-chip encapsulation on ceramic substrate

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3 Author(s)
Tyan-Min Niu ; Div. of Microelectron., IBM Corp., Endicott, NY, USA ; B. G. Sammakia ; S. Sathe

A detailed numerical and experimental study of the thermal-mechanical stress and strain in the solder bumps (C4s) of a flip-chip ceramic chip carrier has been completed. The numerical model used was based upon the finite element method. The model simulated accelerated thermal cycling (ATC) from 0°C to 100°C. Several parametric studies were conducted, including the effects of chip size, micro-encapsulation, and the effect of the presence of voids in the micro-encapsulant. It was notably found that the presence of voids in the encapsulant does not significantly increase the stress/strain in the C4s, with the exception of very large voids and voids at or near the edge of the chip

Published in:

IEEE Transactions on Components and Packaging Technologies  (Volume:22 ,  Issue: 4 )