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A design for test technique to increase the resolution of analogue supply current tests

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2 Author(s)
Chalk, C.D. ; Dept. of Electron. & Comput. Sci., Southampton Univ., UK ; Zwolinski, M.

By employing the new DFT technique proposed here, the fault coverage of the AC RMS supply current test for an opamp within a CMOS analogue multiplier circuit was increased to 100%. The DFTT scheme is based on reducing the width of high current transistors during the test

Published in:

Electronics, Circuits and Systems, 1998 IEEE International Conference on  (Volume:2 )

Date of Conference:

1998