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Finding double Euler trails of planar graphs in linear time [CMOS VLSI circuit design]

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3 Author(s)
Zhi-Zhong Chen ; Dept. of Math. Sci., Tokyo Denki Univ., Saitama, Japan ; Xin He ; Chun-Hsi Huang

The paper answers an open question in the design of complimentary metal-oxide semiconductor (CMOS) VLSI circuits. It asks whether a polynomial-time algorithm can decide if a given planar graph has a plane embedding ε such that ε has a Euler trail P=e1e 2...em and its dual graph has a Euler trail P*=e 1*e2*...em* where ei* is the dual edge of ei for i=1, 2, ..., m. The paper answers this question in the affirmative by presenting a linear-time algorithm

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Foundations of Computer Science, 1999. 40th Annual Symposium on

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