By Topic

Parallel design of a batch-type time-true ATM-network simulator

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Logothetis, M. ; Dept. of Electr. & Comput. Eng., Patras Univ., Greece ; Olivier, M. ; Kokkinakis, G.

This paper presents the parallel design of a new type ATM network simulator. The proposed parallel design is to organize data by virtual paths and then to distribute them among processors, which all execute the same bunch of instructions on these data. The simulator is a pure time-true simulator but it is not a call-by-call type. It is characterized as a batch type. The whole duration of simulation time is divided into short time intervals of equal duration T. During T, a batch processing of events is executed and the time-points of the events are sorted. The number of sorting executions is drastically reduced in comparison to call-by-call simulator, achieving considerable timesaving. Besides, the data structure of the simulator is not only well fitted to parallel processing techniques, for further savings of execution time, but is appropriate for its implementation by a general purpose programming language

Published in:

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on  (Volume:3 )

Date of Conference: