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Power consumption vs. decoding performance relationship of VLSI decoders for low energy wireless communication system design

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2 Author(s)
Sangjin Hong ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; Stark, W.E.

In this paper we investigate power consumption and performance relationships of low complexity VLSI decoders. The study incorporates various representative of decoding algorithms such as turbo-code, block-code, Hadamard code, and convolutional-code. For each of these decoders, its decoding performance and power consumption are estimated from actual implementation. For the turbo-code, a low complexity decoder architecture is presented. The decoder circuit complexities are analyzed in terms of size and power based on 0.6-μm CMOS standard cell technology. This study provides very valuable insights into system design trade-offs involving not only low-power VLSI decoders design but for low energy wireless mobile communication systems

Published in:

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on  (Volume:3 )

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