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A chip design and implementation of a 13-bit high-order oversampling modulator for ISDN-U interface

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3 Author(s)
S. -M. Wu ; Dept. of Electr. Eng., Yuan Ze Univ., Tao-Yuan, Taiwan ; R. -Y. Liu ; Y. -C. Chu

In this paper, presented is a chip design and implementation of a 13-bit, 4th-order with single-bit output oversampling modulator. The signal bandwidth is 80 kHz and the specification meets the ISDN-U interface. An overload detector circuit is designed in VHDL to solve the inherent instability problem in the high-order oversampling modulator. The noise problems and the techniques to improve them are also discussed. While the OSR is 64, the resulting design operates at 10.24 MHz. The SNR is 75.83 dB, the power supply is ±2.5 V, the power consumption is 48.63 mW, and the die area is 1800 μm×1800 μm fabricated in a 0.5 μm CMOS 2P2M process

Published in:

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on  (Volume:3 )

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