A chip design and implementation of a 13-bit high-order oversampling modulator for ISDN-U interface

In this paper, presented is a chip design and implementation of a 13-bit, 4th-order with single-bit output oversampling modulator. The signal bandwidth is 80 kHz and the specification meets the ISDN-U interface. An overload detector circuit is designed in VHDL to solve the inherent instability problem in the high-order oversampling modulator. The noise problems and the techniques to improve them are also discussed. While the OSR is 64, the resulting design operates at 10.24 MHz. The SNR is 75.83 dB, the power supply is /spl plusmn/2.5 V, the power consumption is 48.63 mW, and the die area is 1800 /spl mu/m/spl times/1800 /spl mu/m fabricated in a 0.5 /spl mu/m CMOS 2P2M process.