Optimized system synthesis of complex RT level building blocks from multirate dataflow graphs

In order to cope with the ever increasing complexity of today's application specific integrated circuits, a building block based design methodology is established. The system is composed of high level building blocks, of which some are reused from previous designs while others might have been created by behavioral synthesis. In data flow oriented designs, these blocks usually have complex non-matching interface properties, making it necessary to generate additional interfacing and controlling hardware to integrate them into an operable system. An RTL-HDL code generation from a synchronous data flow representation is introduced, that efficiently automates the generation of the required additional hardware. While existing code generation approaches provide strong limitations concerning the building block interfacing properties, our method enables the integration of components that access their ports periodically with arbitrary patterns. In order to reduce interface register cost, a minimum-area retiming approach is taken to determine optimum building block activation times, which is known to have polynomial time complexity. The code generation methodology is compared to an existing approach using a simple case study