Efficient realization of the M-D nonrecursive filters: from sequential implementation to mapping on systolic array processors

This paper presents algorithms and architectures for implementing from 1-D to multidimensional M-D digital nonrecursive filters. These architectures are very regular and support single chip implementation in VLSI, as well as multiple chip implementations. The proposed systolic arrays, used in implementation of these algorithms, are optimal with respect to time. In a systolic implementation the highest degree of parallel processing and thus performance is achieved. But with this implementation the highest number of gates and thus complexity is obtained. As a compromise, we propose and analyse simpler systolic system for real-time nonrecursive filtering.