By Topic

Efficient realization of the M-D nonrecursive filters: from sequential implementation to mapping on systolic array processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
A. Burian ; Signal Process. Lab., Tampere Univ. of Technol., Finland ; C. Rusu ; P. Kuosmanen

This paper presents algorithms and architectures for implementing from 1-D to multidimensional M-D digital nonrecursive filters. These architectures are very regular and support single chip implementation in VLSI, as well as multiple chip implementations. The proposed systolic arrays, used in implementation of these algorithms, are optimal with respect to time. In a systolic implementation the highest degree of parallel processing and thus performance is achieved. But with this implementation the highest number of gates and thus complexity is obtained. As a compromise, we propose and analyse simpler systolic system for real-time nonrecursive filtering

Published in:

Electronics, Circuits and Systems, 1998 IEEE International Conference on  (Volume:3 )

Date of Conference:

1998