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An analog CMOS realisation of a reconfigurable discrete-time cellular neural network

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3 Author(s)
Brea, V.M. ; Dept. of Electron. & Comput. Sci., Santiago de Compostela Univ., Spain ; Vilarino, D.L. ; Cabello, D.

In this work we propose a new analog CMOS realisation of a cell structure for a Discrete-Time Cellular Neural Network (DTCNN) with a view to implementing a multilayer network for image segmentation based on active contours. Each cell operates in a transresistance manner with a final latch controlled by a single clock phase. The operation with the templates, for the calculation of internal states is provided by voltage programmable current multipliers. The validity of the structure is illustrated by electric HSPICE simulations for an 8×8 DTCNN array, constituted by transistors belonging to the 0.7 μm technology process of ES2

Published in:

Electronics, Circuits and Systems, 1998 IEEE International Conference on  (Volume:3 )

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