By Topic

High speed clock recovery using an optoelectronic phase locked loop implemented with balanced photodetection

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
D. T. K. Tong ; Bell Lab., Lucent Technol., Holmdel, NJ, USA ; B. Mikkelsen ; G. Raybon ; T. N. Nielsen

We have proposed and experimentally demonstrate high-speed clock recovery by employing a novel optoelectronic phase-locked loop. The DC ambiguity caused by the use of optoelectronic phase detector is resolved by balanced photodetection. Low timing jitter of the recovered clock indicates a potential for operation beyond 100 Gb/s using this scheme

Published in:

LEOS '99. IEEE Lasers and Electro-Optics Society 1999 12th Annual Meeting  (Volume:1 )

Date of Conference: