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Clock selection for performance optimization of control-flow intensive behaviors

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2 Author(s)
Khouri, K.S. ; Dept. of Electr. Eng., Princeton Univ., NJ, USA ; Jha, N.K.

This paper presents a clock selection algorithm for control-flow intensive behaviors that are characterized by the presence of conditionals and deeply-nested loops. Unlike previous works, which are primarily geared rewards data-dominated behaviors, this algorithm examines the effects of branch probabilities and their interaction with allocation constraints. We demonstrate, using examples, how changing branch probabilities and resource allocation can dramatically affect the optimal clock period, and hence, the performance of the schedule, and show that the interaction of these two factors must also be taken into account when searching for an optimal clock period. We then introduce the clock selection algorithm, which employs a fast critical-path analysis engine that allows it to evaluate what effect different clock periods, branch probabilities, and resource allocations may ultimately have on the performance of the behavior. When evaluating the critical path, we exploit the fact that our target behaviors exhibit locality of execution. We tested our algorithm using a number of benchmarks from various sources. A series of experiments demonstrates that our algorithm is quickly capable of selecting a small set of performance enhancing clock periods, among which the optimal clock period typically lies. Another experiment demonstrates that the algorithm can adapt to varying resource constraints

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference:

2000

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