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Fast error diagnosis for combinational verification

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2 Author(s)

We address the problem of localizing error sites in a combinational circuit that has been shown to be inequivalent to its specification. In the typical case, it is not possible to identify the error location exactly. We propose a novel diagnosis strategy of gradually increasing the level of detail in the analysis algorithm to ultimately derive a small list of potential error sites in a short time. Our techniques combine the use of simulation, BDDs, and SAT in a novel way to achieve the goal. A limitation of many previous approaches has been that they have been constrained to a specific error model. No such assumption is made in our work. We show through experimental results that these techniques are successful in that the final set of error sites derived is small, contains the actual error sites and is derived in a reasonable amount of time

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference:

2000