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Dataflow analysis for resource contention and register leakage properties

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3 Author(s)
Roy, S.K. ; Fujitsu Labs. Ltd., Kawasaki, Japan ; Iwashita, H. ; Nakata, T.

Resource contention and register leakage are two important classes of properties which need to be verified in every design to identify difficult bugs. They can be derived automatically from the RTL implementation model. In this paper, an approach for their systematic formulation is given. The automated approach unburdens the verification team from the tedious process of formulating them, thereby, allowing focus on the formulation of other important properties

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VLSI Design, 2000. Thirteenth International Conference on

Date of Conference: