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A versatile BIST technique combining test registers and accumulators

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2 Author(s)
F. Mayer ; Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany ; A. P. Stroele

In recent years, many BIST tools have been developed which insert test registers into a circuit at register-transfer level. However, these tools do not exploit all potentialities in test register placement and cause more test overhead than necessary. In this paper we present a versatile BIST technique which overcomes most restrictions of conventional tools. In addition, instead of using only test registers we also allow for accumulators, which have been proven to be a coequal alternative to test registers but with virtually no hardware overhead. The described approach leads to a BIST implementation with minimized hardware overhead and test application time. Various experimental results show considerable savings in test overhead

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VLSI Design, 2000. Thirteenth International Conference on

Date of Conference: