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Resource-constrained compaction of sequential circuit test sets

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3 Author(s)
Bommu, S.K. ; Synopsys Inc., Boston, MA, USA ; Chakradhar, S.T. ; Doreswamy, K.B.

We investigate a new, resource-constrained method for static compaction of large, sequential circuit test sets. Our approach is based on two key observations: (1) since all physical defects cannot be covered using a single defect model, test sets include tests generated using multiple defect models like stuck-at, delay, or bridging fault models. Therefore, it is unlikely that a marginal drop (0.5% or less) in fault coverage during compaction of tests generated for a single defect model will adversely affect the test quality of the overall test set. (2) Fault coverage is an aggregate measure that can be preserved as long as the original and compacted test sets detect the same number of faults. The specific faults detected by the two test sets can be significantly different. In particular, the compacted vector set may detect new faults that are not detected by the original vector set. The new compaction technique was implemented as part of the recently proposed two-phase static compaction technique. Experimental results on ISCAS benchmarks and several production circuits show that: (1) the actual loss in fault coverage, if any, was significantly less than the pre-specified tolerance limit of 1%; (2) fault coverage of the compacted test set can be higher than the original test set; and (3) significantly higher compaction is achieved using fewer CPU seconds, as compared to the baseline system that compacts test sets to preserve fault coverage

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference:

2000

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