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Architecture and implementation of a high-definition video co-processor for digital television applications

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4 Author(s)
Dutta, S. ; Philips Semicond., Sunnyvale, CA, USA ; Singh, D. ; Abu-Ghoush, E. ; Mehra, V.

This paper describes the architecture, functionality, and design of HDVO-a high definition video co-processor from Philips Semiconductors. The coprocessor design is modular and functionally complete, and is intended to be a part of and function as the primary picture/video composition hardware in any media-processor chip targeted at Digital Television (DTV) applications. Essentially a screen-refresh engine, HDVO can mix multiple video and graphics planes and is capable of scaling vertically and horizontally pictures of the highest resolution (1920×1080) specified in the DTV standard prescribed by the United States Advanced Television Systems Committee (ATSC). HDVO can efficiently process all (eighteen) ATSC video formats, including video generation for picture-in-picture display, and is currently being wed as an on-chip video coprocessor in the TM-2700 digital television chip. TM-8700 is the second generation of an architectural family of programmable multimedia processors from Philips Semiconductors and it not only supports all ATSC formats, from standard-definition to wide-angle high-definition video, but has also the power to handle High-Definition Television (HDTV) video and audio source decoding (high-level MPEG-2, AC-3 and ProLogic audio, closed captioning, etc.) as well as the flexibility to process advanced interactive services

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference:

2000