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Optimisation of the one-dimensional full search algorithm and implementation using an EPLD

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2 Author(s)
R. T. N. Rajaram ; Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India ; V. Vasudevan

This paper presents a technique for the modification and optimisation of the one-dimensional full search (IDFS) motion estimation algorithm. The modified version of the IDFS algorithm has desirable properties for efficient hardware implementation. The spatial redundancy between the motion vectors of the macroblocks within a frame is exploited for the purpose of optimisation. The performance of the proposed technique is competitive, as compared to the more popular hierarchical three step search (TSS) method. The speed of the proposed technique, when implemented in hardware, is higher than the TSS method. The results of an implementation in an EPLD, targeted for real time operation, are given

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VLSI Design, 2000. Thirteenth International Conference on

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