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Automatic validation test generation using extracted control models

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3 Author(s)
R. Sumners ; Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA ; J. Bhadra ; J. Abraham

We present a procedure for the automatic generation of tests covering control states of a sequential circuit. The procedure consists of extracting a control model of the circuit under test and then using this model to guide the search for concrete executions or witnesses. We present results of experiments using the procedure on a communication chip from industry as well as an implementation of the ARM 2 processor

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VLSI Design, 2000. Thirteenth International Conference on

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