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Design for strong testability of RTL data paths to provide complete fault efficiency

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4 Author(s)
H. Wada ; Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Ikoma, Japan ; T. Masuzawa ; K. K. Saluja ; H. Fujiwara

In this paper, we propose a DFT method for RTL data paths to achieve 100% fault efficiency. The DFT method is based on hierarchical test and usage of a combinational ATPG tool. The DFT method requires lower hardware overhead and shorter test generation time than the full scan method, and also improves test application time drastically compared with the full scan method

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference:

2000