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Routing on switch matrix multi-FPGA systems

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2 Author(s)
A. Ejnioui ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; N. Ranganathan

In this paper, we address the problem of routing nets on multi-FPGA systems interconnected by a switch matrix. Switch matrices were introduced to route signals going from one channel to another inside the FPGA chips. We extend the switch matrix architecture proposed by Zhu et al. (1993) to route nets between FPGA chips in a multi-FPGA system. Given a limited number of routing resources in the form of programmable connection points within the two-dimensional switch matrix, this problem examines the issue of how to route a given net traffic through the switch matrix structure. First we formulate the problem as a general undirected graph in which each vertex has one single color. Since there can be at most six colors in the entire graph, the problem is defined as a search for at most six independent vertex sets of each color in the graph. We propose an exact solution for this problem that is suitable only for small size switch matrices. For large size switch matrices used in multi-FPGA systems, we convert the graph-theoretic formulation to a constraint satisfaction problem. Due to its large size, we then model the constraint satisfaction problem as a 0-1 multi-dimensional knapsack problem for which a fast approximate solution is applied. Experiments were conducted on switch matrixes of various sizes to measure the performance of the proposed approximate solution. The results show that the performance of our proposed heuristic improves with the increasing size of the switch matrixes

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VLSI Design, 2000. Thirteenth International Conference on

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