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Manufacturability and testability oriented synthesis

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3 Author(s)
Shaikh, S.A. ; DFM Group, Level One Commun. Inc., Sacramento, CA, USA ; Khare, J. ; Heineken, H.T.

This paper presents a case for new generation synthesis tools that incorporate manufacturability and testability as optimization factors in addition to traditional factors such as timing, die-area, and power. A suitable approach for manufacturability oriented synthesis is the interconnect field model, which estimates yield as a function of netlist attributes. Testability oriented synthesis encompasses various design-for-test (DFT), synthesis for testability, (SFT) and the high-level test synthesis (HLTS) techniques during the synthesis process

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VLSI Design, 2000. Thirteenth International Conference on

Date of Conference: