Manufacturing and test considerations in system-on-chip designs

In order to take costs into account, there needs to be proper cost models at every stage in the design cycle. These cost models must be able to compute SoC cost in terms of design characteristics that are available at the given design stage. This session describes the impact of cost at four stages in the design cycle: (a) architecture; (b) synthesis; (c) layout; and (d) test. This will be done using data from example industrial SoCs. In addition, methodologies to reduce costs at each of these three stages will be proposed.