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A methodology for the placement and optimization of decoupling capacitors for gigahertz systems [CMOS VLSI]

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5 Author(s)
J. Choi ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; S. Chun ; N. Na ; M. Swaminathan
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This paper discusses a method for computing the effect of decoupling capacitors on the power delivery system for gigahertz packages and boards. A fast and accurate computational method is presented that can be used to estimate the amount of decoupling required, the type of capacitor to be used and its location (on-chip, package or board)

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference:

2000