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Interconnect statistical modeling, structures and measurement methodology

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1 Author(s)
Doganis, A. ; Mentor Graphics, San Jose, CA, USA

Today, ICs are fabricated with increasingly more metal layers as well as more routing on each layer. Interconnects have become the most crucial factor of signal delays, especially, in deep and very deep submicron designs. To accurately predict the circuit performance, the need of accurate, fast, and scalable interconnect models is necessary at all stages of the circuit analysis. High performance, and accurate silicon calibration for interconnect and active devices using specialized test structures are essential at 0.25 micron and below. In this work, we introduce a minimal set of interconnect test structures along with the measurement scheme and the associated extraction methods. On-chip measurements of such simple structures will be used for calibration of field solvers and interconnect extraction tools. Measurements from complex structures such as clock nets, I/O's, standard cells, will farther refine the generated parasitic interconnect models. Those empirical models are simple, accurate, compact and process independent. They are calibrated and optimized for the particular location process via field solver simulations in connection with on-chip test structure measurements. Additionally, process variations measured from specialized test structures are taken into account in both during the calibration of the field solver as well as the generation of the interconnect compact models. This is achieved by using the principal component analysis (PCA) and circuit performance response surface models (RSM) to derive statistically meaningful interconnect models for “corner” or “statistical worst case” analysis which are appropriate for xCalibre. Yield maximization, design centering and design for interconnectivity will follow as a natural step in improving the circuit performance. Furthermore, measurements from 0.25, 0.18, and 0.15 micron technologies, will create a delay, and performance surface model which will, in the first order predict the delays and performance for 0.12 designs and beyond

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference:

2000