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Scalable pipelined micro-architecture for wavelet transform [image compression]

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3 Author(s)
Paul, K. ; Dept. of Comput. Sci. & Technol., Deemed Univ., Agra, India ; Roy Chowdhury, D. ; Pal Chaudhuri, P.

A new scalable pipelined micro-architecture has been proposed for evaluating the discrete wavelet transform which demands very high processing power. The proposed scheme does away with the explicit multiply operation which is both expensive as well time consuming and provides an innovative method to obtain the transformed values of the discrete samples at every clock cycle

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference:

2000

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