By Topic

Relating data characteristics to transition activity in high-level static CMOS design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Henning, R. ; Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA ; Chakrabarti, C.

Significant power reduction can be obtained in the datapath of a CMOS VLSI circuit if data characteristics are carefully exploited. An improved approach that achieves such reduction by using a new model relating important data characteristics to the transition activity in static CMOS circuits is presented. Specifically, relationships between fixed-point, two's complement data and 0→1 transition activity in static CMOS circuits are identified. Models for computing transition activity in terms of a set of statistical parameters are developed, and their performance compared with the Dual Bit Type model. Then, the use of the relationships and models to analyze and significantly reduce 0→1 transition activity with little computational effort is illustrated by several, high-level synthesis examples

Published in:

VLSI Design, 2000. Thirteenth International Conference on

Date of Conference: