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An assertion based technique for transistor level dynamic power estimation

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3 Author(s)
Savithri, S. ; Motorola India Electron. Ltd., Bangalore ; Venkatesan, R. ; Bhaskar, S.

With increasing complexity of submicron designs, transistor level power estimations and analyses have become a necessity. Power conscious synthesis and optimizations are critical aspect of design flow These require a fast approach to estimate average power and predict the upper bound. A novel assertion based approach for predicting worst dynamic power dissipation is presented here. This technique models all signal correlations within the design. It maximizes loading conditions using assertions to predict maximum power. An Elmore model is used for calculating delay-based power estimates. The technique allows for quick prediction of the power dissipated in the design without loss of much accuracy. It does not need any elaborate circuit simulation iterations. The input pattern dependence is eliminated using the Monte-Carlo approach

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VLSI Design, 2000. Thirteenth International Conference on

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