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Low voltage low power CMOS design techniques for deep submicron ICs

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3 Author(s)
Liqiong Wei ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; K. Roy ; V. K. De

Due to the quadratic reduction in the switching power dissipation, lowering supply voltage is obviously one of the most effective ways to reduce power consumption. However, the performance will degrade. In order to satisfy the high performance requirements, threshold voltage has to be scaled. Unfortunately, such scaling leads to a dramatic increase in leakage current, which becomes a new concern for low voltage and high performance circuit designs. Multiple transistor threshold and supply voltages can be used to achieve low power and high performance while maintaining low leakage current. In this tutorial, different multiple-Vth, multiple-Vdd and standby leakage control techniques are presented

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VLSI Design, 2000. Thirteenth International Conference on

Date of Conference: