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Static and dynamic test sequence compaction methods for acyclic sequential circuits using a time expansion model

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4 Author(s)
Hosokawa, T. ; Div. of Corp. Semicond. Dev., Matsushita Electr. Ind. Co. Ltd., Osaka, Japan ; Inoue, T. ; Hiraoka, T. ; Fujiwara, H.

Test sequences for acyclic sequential circuits can be generated using a time expansion model. The test sequences have features that: (1) the length of each test sequence for each target fault is uniform, and (2) positions of `don't cares' (X) of each test sequence for each target fault are independent of any target fault. In this paper, focusing on the features, we present two test sequence compaction methods: static compaction and dynamic compaction. The static test sequence compaction method uses a template. The dynamic test sequence compaction method uses a reverse transformation fault simulation: a fault simulation for a time expansion model with test patterns into which test sequences are reversely transformed after the static compaction. Experimental results for some acyclic sequential circuits show that the compaction methods reduce the number of test patterns by 66% to 81%

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Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian

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