By Topic

An effective methodology for mixed scan and reset design based on test generation and structure of sequential circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hsing-Chung Liang ; Dept. of Electron. Eng., Chang Gung Univ., Tao-Yuan, Taiwan ; Chung Len Lee

In this paper, a flip-flop selection methodology, which utilizes reachable states of flip-flops, required states for hard-to-detect faults, which are obtained from test generation, and the structural connection relationship of flip-flops, to achieve a nearly optimal mixed partial-scan/reset design, is proposed. The methodology first generates and simulates test patterns for the circuit-under-test to obtain information of reachable states and states needed for excitation and propagation of hard-to-detect faults. It then searches the connection relationship among flip-flops and arranges flip-flops in an appropriate order for mixed partial scan and reset selection. Experimental results show that the method achieves higher testability than reported methods with a lesser number of scan/reset flip-flops

Published in:

Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian

Date of Conference: