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Automatic test pattern generation for improving the fault coverage of microprocessors

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3 Author(s)
Hirase, J. ; Matsushita Commun. Ind. Co. Ltd., Japan ; Yoshimura, S. ; Sezaki, T.

In order to improve the quality of microprocessor tests, the use of instruction sets for testing is indispensable. In this paper, we will present a new method consisting of the automatic generation of a functional test pattern, formed by a combination of instructions sets and enabling the efficient improvement of the fault coverage. With this method, a test pattern is first generated to test all of an S number of instruction mnemonics. Then, for the faults that were undetected by that test pattern, an L number of sets of K number of instructions are drawn from the S number of instructions, and the set enabling the efficient improvement of the fault coverage is selected. By repeating this procedure, a high fault coverage can be obtained with a short test pattern. The effectiveness of our method was proved by the results of experiments obtained with the software that was created based on this method

Published in:

Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian

Date of Conference:

1999