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Techniques for improving the efficiency of sequential circuit test generation

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3 Author(s)
Xijiang Lin ; Mentor Graphics Corp., Wilsonville, OR, USA ; I. Pomeranz ; S. M. Reddy

New techniques are presented in this paper to improve the efficiency of a test generation procedure for synchronous sequential circuits. These techniques aid the test generation procedure by reducing the search space, carrying out non-chronological backtracking, and reusing the test generation effort. They have been integrated into an existing sequential test generation system MIX to constitute a new system, named MIX-PLUS. The experimental results for the ISCAS-89 and ADDENDUM-93 benchmark circuits demonstrate the effectiveness of these techniques in improving the fault coverage and test generation efficiency.

Published in:

Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 1999